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What are the characteristics of 8051 single-chip microcomputer? What are the control bus signals of 8051 single-chip microcomputer?

September 18, 2020


Features of 8051 MCU

   The 8051 command system consists of 111 commands. If classified according to the number of bytes, there are 49 single-byte instructions, 46 double-byte instructions and 16 three-byte instructions, mainly single-byte instructions; if classified according to instruction execution time, there are 64 single-cycle instructions, 45 double-cycle instructions and 2 four-cycle instructions, with single-cycle instructions being the main ones.


The command system of 8051 has the following characteristics:

       (1) High storage efficiency, fast execution speed, data transfer from direct address to direct address, and the content of a parallel I/O port can be transferred to the internal RAM unit without going through the accumulator A or the working register Rn. This can greatly increase the transmission speed and alleviate the bottleneck effect of the accumulator A.

   (2) Use indexed addressing to access the table in the program memory, and transfer the fixed constant or table byte content in the program memory unit to the accumulator A. This provides convenience for compiling translation algorithms.

   (3) There are multiplication and division instructions in the arithmetic operation instructions

   (4) In the command system, some commands that operate on the I/O port have the function of "read-modify-write". This function means: when executing the instruction to read the latch, the CPU first completes the value of the latch into the internal through the buffer BUF2, modify, change, and then rewrite to the latch. This type of instruction includes all logic operations and bit manipulation instructions.

What are the control bus signals of 8051 microcontroller

   (1) ALE/(/PROG): Address latch enable/program line, used with the second function of P0 port pin. When accessing the off-chip memory, the 8051CPU outputs the low 8-bit address of the off-chip memory on the P0.7~P0.0 pins, and at the same time outputs a high potential pulse on ALE/(/PROG) to use this off-chip memory The low 8-bit address is latched to the external dedicated address latch, so as to free the P0.7 ~ P0.0 pin line to transmit the subsequent off-chip memory read and write data. When not accessing the off-chip memory, the 8051 automatically outputs a pulse sequence with a frequency of fosc/6 on ALE/(/PROG). This pulse sequence can be used as an external clock source or as a timing pulse source.

  (2) (/EA)/Vpp: Allows access to off-chip memory/programming power line, and can control whether 8051 uses on-chip ROM or off-chip ROM. If (/EA)=0, on-chip ROM is allowed; if (/EA)=1, off-chip ROM is allowed.

  (3) (/PSEN): Off-chip ROM strobe line. When executing the instruction MOVC to access off-chip ROM, the 8051 automatically generates a negative pulse on (/PSEN), which is used to gate the off-chip ROM chip. In other cases, the (/PSEN) line is in a high-level blocked state.

   (4) RST/VPD: Reset/standby power line, which can make 8051 in reset state.