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Top 26 Common Mistakes in Electronic Circuit Design, You Can Avoid Now

July 02, 2019

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I will list 26 common mistakes in electronic circuit design that every new electronic engineers will make, from 5 aspects, besides, it also attach the related solutions for each mistake.

Let’s start....

Misunderstanding 1: Cost Savings

Here I will list 6 electronic circuit design mistakes from saving cost. Details are as followed:

Common Mistake 1: What color I should choose for the indicator on the panel? I personally like blue, just choose it.

Solution: For the indicator lights on the market, the colors such as red, green, yellow and orange, regardless of the size (below 5MM) and packaging, they have matured for decades, so the price is generally less than 5 cents. But, the blue indicator light was invented in the past three or four years, and the technical maturity and supply stability are poor, so the price is four or five times more expensive. If you design a panel stack indicator color without special requirements, it's suggested you do not choose blue. At present, the blue indicator light is generally only used when it cannot be replaced by other colors, such as displaying a video signal.

Common Mistake 2: These pull-down / pull-up resistors, there is not requirment for specific resistance values , so  choosing resistance 5K is ok.

Solution: In fact, there is no 5K resistance value in the market, the closest is 4.99K (accuracy 1%), followed by 5.1K (accuracy 5%), and its cost price is 4 times higher than the accuracy of 20% 4.7K and 2 times. The resistance of 20% precision only cptain the following categories: 1, 1.5, 2.2, 3.3, 4.7, 6.8 (including integer multiples of 10). Correspondingly, the capacitance of 20% precision is also the same as the above values. For resistors and capacitors, if you choose a other value not these values, you must use higher accuracy and the cost will be higher. If the accuracy requirements are not large, this is a waste of cost. In addition, the quality of the resistor is also very important. Sometimes a group of inferior resistors is enough to destroy a project. It is recommended that you buy it in a genuine self-operated mall such as Censtry.


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Common Mistake 3: This logic is also used with the 74XX gate circuit, but it is too earthy. It's suggested you use CPLD, it looks more upscale.

Solution: 74XX's door circuit is only a few cents, and CPLD is at least tens of dollars (GAL/PAL is only a few dollars, but it is not recommended). The cost has been increased many times, and it is still given to production, documentation, etc. add several times the work. It is obviously more appropriate to use the 74XX with higher cost performance without affecting performance.

Common Mistake 4: The PCB design requirements of this board are not high, you can just use a thin line and automatically cloth it.

Solution: Automatic routing must occupy a larger PCB area, and at the same time it produces more than many times more than manual wiring. In the large batch of products, PCB manufacturers in terms of pricing, line width, the number of vias are important consideration factors, because they affect the PCB yield and the consumption of the drill bit, in addition, the area of the PCB is also affecting the price.Therefore, automatic wiring is bound to increase the production cost of the circuit board.

Common Mistake 5: Our system requirements are so high, therefore, the chips we chosen should be the fastest, including  MEM, CPU, FPGA etc.

Solution: In a high-speed system, not every part works at high speed, and every time the device speed is increased by one level, the price is almost doubled, and it also has a great negative impact on signal integrity issues. Therefore, when selecting a chip, it should be considered according to the degree of use of different parts of the device, rather than the fastest.

Common Mistake 6: As long as the program is stable, longer code  and the low efficiency  are not critical.

Solution: CPU speed and memory space are all bought with money. If you spend a few days to improve the efficiency of the program when writing code, then the cost saved by reducing the CPU frequency and reducing the memory capacity is definitely cost-effective. The CPLD/FPGA design is similar.

Misunderstanding 2: Reliability Design

Here I will list 3 electronic circuit design mistakes from reliability design. Details are as followed:

Common Mistake 7: Users can't blame me for problems with operating mistakes.

Solution: It is correct to require the user to operate strictly according to the manual. However, when the user is a human being, they also make mistakes. It cannot be said that if a wrong key is touched, it will crash, and if a wrong plug is inserted, the board will be burned. Therefore, various mistakes that users may make must be predicted and protected in advance.

Common Mistake 8: The reason for the bad board is that the board on the opposite side has a problem, and it is not my responsibility.

Solution: There should be sufficient compatibility for various external hardware interfaces. You can't completely strike because the other party's signal is not normal.

It should only affect the part of the function that is related to it, but other functions should work properly, should not be completely striked, or even permanently damaged, and once the interface is restored, you should immediately return to normal.

Common Mistake 9: This part of the circuit is designed to be free of problems as long as it requires software.

Solution: Many device features on the hardware are directly controlled by software, but when software is often buggy and the program runs away, it is impossible to predict what will happen. The designer should ensure that no permanent damage is caused in a short period of time, regardless of the hardware in which the software is operated.

Misunderstanding 3: System efficiency

Here I will list 6 electronic circuit design mistakes from system efficiency. Details are as followed:

Common Mistake 10: Is so many tasks using interrupts or queries? I think it's still interrupt faster.

Solution: The real-time nature of the interruption is strong, but it’s not necessarily fast. If there are a lot of interrupted tasks, this does not quit, thenit will follow, finally, the system will crash in a while.If the number of tasks is large and very frequent, the CPU's great effort is spent on the cost of incoming and outgoing interrupts, and the system efficiency is extremely low. If the query method is used instead, the efficiency can be greatly improved, but the query sometimes cannot meet the real-time requirement. Therefore, the best way is to interrupt query , that is, you can exit, after all the interrupts are processed and all the accumulated tasks are processed.

Common Mistake 11: This CPU with a frequency of 100M can only handle 70%, and it is fine to change the 200M frequency.

Solution: The processing power of the system involves a variety of factors. In the communication service, the bottleneck is generally in the memory but if the CPU is fast internal, and the external access is not fast.

Common Mistake 12: using a CPU with a larger CACHE, it should be faster.

Solution: The increase of CACHE does not necessarily lead to an increase in system performance. In some cases, system performance is faster than using CACHE by closing CACHE. The reason is that the data moved to CACHE must be reused multiple times to improve system efficiency. Therefore, in the communication system, only the instruction CACHE is generally opened, and even if the data CACHE is opened, it is limited to a part of the storage space, such as the stack portion. At the same time, the program design also needs to take into account CACHE's capacity and block size. This involves the length and jump range of the key code loop body. If a loop is just a little bigger than CACHE, and it is looping repeatedly, it will be troublesome.

Common Mistake 13: The timing of the memory interface is the factory default configuration, you don't need to modification.

Solution: The default values set by the BSP for the memory interface are set according to the most conservative parameters. In practical applications, parameters such as bus operating frequency and waiting period should be properly allocated. Sometimes, Low frequency can increase the efficiency. For example, if the RAM access period is 70 ns and the bus frequency is 40 M, you can set the access time of 3 cycles, that is, 75 ns. If the bus frequency is 50 M, it must be set to 4 Cycles,  and the actual access time has slowed down to 80ns.

Common Mistake 14: This CPU has a DMA module, and it is certainly faster to use it to move data.

Solution: The real DMA is to start the two terminals at the same time after the hardware grabs the bus, and read it in one cycle. But many DMAs embedded in the CPU are just simulations. You need to do a lot of preparation before starting each DMA (set the start address and length, etc.) In the transmission, it is often read into the chip for temporary storage, then write out, that is, it takes two clock cycles to move the data, which is faster than the software. (No need to fetch instructions, no extra work such as loop jumps), but if you only move a few bytes at a time, you still have to do a bunch of preparations, usually involving function calls, and the efficiency is low.

So this kind of DMA is only applicable to big data blocks, don't use it blindly.

Common Mistake 15: When a CPU can't handle it, it uses two distributed for processing, and the processing power can be doubled.

For moving bricks, two people should be twice as efficient as one person; but for painting, one person will cause low efficiency. The use of several CPUs requires more knowledge of the business before it can be determined, that is, to minimize the cost of coordination between the two CPUs, so that 1+1 is as close as possible to 2,  not less than 1.

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Misunderstanding 4: Low power design

Here I will list 8 electronic circuit design mistakes from low power design. Details are as followed:

Common Mistake 16: These bus signals that are pulled with a resistor will be better.

Solution: There are many reasons why the signal needs to be pulled up and down, but not all of them have to be pulled. The pull-down resistor pulls a simple input signal, and the current is below tens of microamperes, but pulling a driven signal that will have a current of milliamperes. The current system is usually 32 bits of address data, and there may be 244/245 isolated bus and other signals. If they are pulled up, the power consumption of several watts is consumed by these resistors. (Do not use the concept of 8 cents a power to treat the power consumption of these watts, the reason is to as followed).

Common mistake 17: Our system is powered by 220V, so we don't care about power consumption.

Solution: Low-power design is not just to save power, but more to reduce the cost of power modules and cooling systems. The reduction of current also reduces the interference of electromagnetic radiation and thermal noise. As the temperature of the device decreases, the lifetime of the device increases accordingly (for every 10 degrees increase in the operating temperature of the semiconductor device, the lifetime is reduced by half). Power consumption issues must be considered at all times.

Common Mistake 18: The power consumption of these small chips is very low, there is no need to consider.

Solution: It is difficult to determine the power consumption of the chip that is not too complicated inside. It is mainly determined by the current on the pin. An ABT16244 consumes less than 1 mA without load, but its indicator is that each pin can be driven. 60 mA load (such as a resistor matching tens of ohms), that is, the maximum power consumption can reach 60*16=960mA. Of course, only the power supply current is so large, and the heat is falling on the load.

Common mistake 19: How to deal with these unused I/O ports of CPU and FPGA? Let it be empty and deal with it later.

Solution: If the unused I/O port is floating, it may become an input signal of repeated oscillation due to a little interference from the outside, and the power consumption of the MOS device basically depends on the number of times the gate circuit is flipped. If you pull it up, each pin will also have a micro-ampere current, so the best way is to set it as an output (of course, you can't connect other driven signals outside).

Common Mistake 20: There are so many doors left in this FPGA that you can use it as much as possible.

The power consumption of FGPA is proportional to the number of flip-flops used and the number of flips, so the power consumption of the same model of FPGA at different times of different circuits may differ by a factor of 100. Minimizing the number of flip-flops at high speeds is the fundamental way to reduce FPGA power consumption.

Common mistake 21: The memory has so many control signals. I only need to use the OE and WE signals on this board. The chip selection is grounded, so the data is much faster when reading.

Solution: The power consumption of most memories will be more than 100 times larger when the chip select is valid (regardless of OE and WE), so CS should be used to control the chip as much as possible. It is possible to shorten the width of the chip select pulse, when all other requirements should be met.

Common Mistake 22: Reducing power consumption is a matter for hardware personnel, and it doesn't matter with software.

Solution: the hardware is just a stage, the software is singing. The access of almost every chip on the bus and the flip of each signal is almost controlled by software. If the software can reduce the number of external accesses (use more register variables, use more internal CACHE, etc.), respond to interrupts in a timely manner (interrupts are often active low with pull-up resistors) and other specific measures for specific boards Both will make a big contribution to reducing power consumption. In order to make the board turn well, the hardware and software must be grasped by both hands!

Common Mistake 23: How do these signals have an overshoot? As long as the match is good, it can be eliminated.

Solution: Except for a few specific signals (such as 100BASE-T, CML), there are overshoots. As long as they are not very large, they do not necessarily need to match, even if the match is not the best match. The output impedance like TTL is less than 50 ohms, and some even 20 ohms. If such a large matching resistor is used, the current is very large and the power consumption is unacceptable, in addition, the signal amplitude will be too small to be used. Besides, the output impedance of the general signal at the output high level and the output low level is not the same, and the method is completely matched. Therefore, the matching of signals such as TTL, LVDS, and 422 can be accepted as long as the overshoot is acceptable.

Misunderstanding 5: Signal Integrity

Here I will list 3 electronic circuit design mistakes from signal integrity. Details are as followed:

Common Mistake 24: These signals have been simulated, and they are certainly no problem.

Solution: The simulation model cannot be exactly the same as the real thing, even the physical objects processed in different batches are different, so as to the model. Besides, the actual situation is very different, and simulation is not likely to exhaust all possibilities, especially crosstalk. There is a lesson that a board has a packet of a certain length and is easy to drop packets. The last reason is that the value of the length field is 0xFF. When this data appears on the bus, it interferes with the adjacent WE signal, causing the write to not enter the RAM. Other data will also interfere with WE, but the interference is within an acceptable range, but when the 8-bit bus is simultaneously 0-edge 1, the nearby signal can't stand. The conclusion is that the simulation results are for reference only.

Common Mistake 25: To ensure a clean power supply, the de-capacitor is much better.

Solution: In general, the more the decoupling capacitors, the better the power supply will be, but there are too many disadvantages: waste of cost, difficulty in wiring, and too much power-on current. The key to the design of the decoupling capacitor is to select the pair of capacitors and place them in the right place. The general chip manuals have a design reference for the decoupling capacitors. It is best to follow the manual.

Common Mistake 26: Since it is a digital signal, the edge is of course as steep as possible.

Solution: The steeper the edge, the wider the spectrum range, and the higher the energy of the high-frequency part; the higher the frequency, the easier the signal will be radiated (for example, a microwave radio can be made into a mobile phone, and many long-wave radio stations cannot do it) The easier it is to interfere with other signals, however, the worse the quality of the transmission on the wire becomes. Therefore, low-speed chips can be used as much as possible with low-speed chips.

Conclusion

I believe many new engineers have similar ideas when designing electronic circuits. All are the engineering mistakes I collected from my work. If there is any new or left one, please let me know by make comments.