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Multi-channel RF to data development platform helps phased array prototype development

June 17, 2021


The industry development trend of antenna design in the future is to adopt phased array. This technology trend, coupled with time-to-market pressure, has resulted in a shortened development time problem, which has brought many challenges to RF designers in the field of phased array systems. Challenges related to RF electronics include:

Validation of RF electronics in a multi-channel environment

Verify synchronization and calibration across multiple channels

Software development and mass production hardware development in parallel

In order to solve these industry challenges, a new type of multi-channel RF to data development platform came into being. This development platform integrates a software-configurable data converter, RF distribution, power adjustment and clock to provide a 16-channel, S-band direct sampling solution.

Integrated RF sampling high-speed converter

ADI's high-speed converter integrates ADC, DAC and digital signal algorithm modules on a single chip. The MxFE™ four-channel 16-bit, 12 GSPS RF DAC and four-channel 12-bit, 4 GSPS RF ADC shown in Figure 1 are an example, including 4 ADCs, 4 DACs, multiple digital up/down converters, and Numerically controlled oscillator (NCO) and finite impulse response (FIR) digital filter. The sampling rate of the DAC is 12 GSPS, and the sampling rate of the ADC is 4 GSPS. The analog bandwidth provides direct sampling and waveform generation in the S-band, and enters the low C-band.

The converter handles a wider range of RF spectrum bands and embeds on-chip DSP functions, enabling users to configure programmable filters and digital up-conversion and down-conversion modules to meet specific RF signal bandwidth requirements. Compared with an architecture that performs these functions in an FPGA, implementing embedded processing in a dedicated chip can significantly reduce power. Freeing up valuable FPGA resources enables designers to use FPGAs more cost-effectively, or allocate FPGA resources to higher-level system application processing.

16-channel, direct RF sampling development platform (four MxFE)

This 16-channel, direct RF sampling development platform launched by ADI is shown in Figure 2, and its block diagram is shown in Figure 3. To illustrate its naming convention: we named the integrated converter mixed-signal front end (MxFE), and the 16-channel board containing 4 MxFEs was named quad MxFE. Each of the 4 MxFEs contains 4 DACs and 4 ADCs, so there are a total of 16 transmit channels and 16 receive channels.

The RF part includes baluns, amplifiers and filters, which can simplify the RF interface. The transceiver channel contains a low-pass filter to suppress the DAC image, and the DAC output generally has a gain block. The receiver channel contains two gain and gain controls, as well as a bandpass filter for second-order Nyquist sampling. The filter adopts Mini-Circuits' 1206 filter size, so users can adapt to different applications by replacing the filter.

The channel spacing is 600 mils for each transmitter/receiver pair, and supports X-band, half-wavelength, and single-pole element grid spacing. With this size, the design shows that each unit digital beamforming system can be compatible with frequencies up to X-band. In the case that the four MxFE directly generates the S-band, a single RF mixer can be additionally added to realize the X-band frequency operation.

It contains clock circuits, and all clocks use the same reference frequency. The PLL of each converter is phase-locked to the reference frequency and provides the AD9081 clock input. Contains test point injection options to evaluate alternate converter clock sources. The digital clock also uses the same reference frequency. A clock chip provides the SYSREF signal for the AD9081 for synchronization, provides the required clock signal for the FPGA, and provides the option of providing the reference frequency for the AD9081 to use the internal PLL of the AD9081.

Power distribution and voltage regulation are shown in Figure 4. All the required voltage is derived from a single 12 V input. The power distribution design includes a combination of switching regulators, followed by a low-noise linear regulator to provide noise-sensitive analog voltages.




Software control

The developed software, firmware, and FPGA code realize platform control through higher-level processing languages. MATLAB® scripts and GUI enable system engineers to develop models that can be directly connected to the hardware in the MATLAB environment. The MATLAB interface supports the evaluation of user-defined waveforms directly in the hardware. The received data capture interface supports user-specific received data processing.

The software and firmware are open source, similar to other ADI modules based on our new transceivers or converters.

in conclusion

Four MxFE RF in place development platforms help to realize a common prototyping environment. Its functions include:

Multi-channel synchronous development platform across multiple converter ICs and boards.

Before the customer, the multi-channel performance was verified through the evaluation board environment, instead of developing a mass production design for the sole purpose of testing multiple channels at the same time.

Highly integrated and functional, it supports simultaneous implementation of software development and hardware production.

These functional combinations can eliminate the prototyping steps in the development of multi-channel RF system products, allowing RF engineers to use existing implementations and concentrate on developing system solutions. The RF to data development platform was initially planned to support phased array development. However, its versatility allows it to be used in multi-channel RF systems such as radar, EW, 5G, and instrumentation applications. As a result, a single-hardware, multi-application platform has been developed, which can provide a truly software-defined multi-channel environment.