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Intel advanced 3D packaging technology interpretation

May 19, 2020

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Earlier, we reported on TSMC's work, including CoWoS for high-end performance applications, the extensive InFO package process family, and their 3D IC stack SoIC demo.Similarly, Intel's advanced packaging portfolio includes its 2.5d EMIB and face-to-face 3D stack Foveros technology.More recently, the company added co-emib, combining the two into a more complex chip.


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The embedded multiple interconnect bridge (EMIB) has many obvious advantages over the traditional silicon interconnect layer.Embedding a small piece of silicon where needed on a large intermediary layer has a significant cost advantage.The first-generation EMIB products have been shipping for some time among a number of products, including the company's high-end Stratix X FPGA and Kaby Lake G mobile chips


By the beginning of last year, Intel had sold more than a million emib-based products.Because these are super advanced products, it is unlikely that the technology costs will be spread to amortize the cost of the technology, but as the technology starts to ship in more products, it will be enough to improve it.Like EMIB, Foveros can provide a larger bump density increase, but it does so by stacking two bare pieces face to face, making it more expensive


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Both EMIB and Foveros have their strengths, but they are far from perfect.


In the case of Foveros, it provides high bandwidth between the top and bottom die.In order to power the top die, a hole must be placed through the bottom die.TSV will increase the resistance, although the resistance can be reduced by adding more holes, but it will increase the area cost.


Most importantly, the exclusion of zones and the inherent increase in existing routing congestion have exacerbated the situation.According to Intel, the conservative estimate is a 20% increase in chip size.In some cases it can be as high as 70%.Then there is heat dissipation.Heat dissipation is a major concern for high performance applications, as the die above blocks the path of the fin, increasing thermal resistance.


Traditional silicon interlayer can avoid this problem by distributing bare pieces on large pieces of silicon, thus achieving better cooling effect.Also, it eliminates the need for TSV in logic chips, so it does not affect area utilization.A larger mediation layer adds to the cost.In addition, the 2.5d solution loses the advantage of 3D encapsulation.This is where Intel's ODI technology comes in.


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Omnidirectional interconnection (ODI) is a new package interconnection technology.This is another tool in the growing encapsulation selection library that can be leveraged where appropriate.ODI Bridges the gap between EMIB and Foveros through a number of 3D packaging processes that enhance power transfer and cooling capabilities over alternatives such as silicon intermediation layers.


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ODI currently has four variants.There are two main options, "type 1" and "type 2".There are two different choices for each type -- copper pillar vs. cavity.All four variants can be combined as needed.Similarly, the bottom ODI chip can be an active chip, a passive chip, or a combination of both.


In ODI type 1, the die is placed under two top dies, or under a single die that does not completely cover the bottom die.In ODI1, the bottom chip only covers the top chip that needs bonding, which inherits the advantages of foveros-like interconnection and eliminates the disadvantages of TSV.ODI1 can be passive, such as when performing simple routing between individual bare chips, or active, such as when actively routing data between multiple bare chips or providing a highly localized cache directly under multiple bare chips.This type of chip can also be used for a single chip, such as a processor with HBM or other logic.


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For high-performance applications with a greater focus on heat, ODI1 offers the added advantage of standard 2.5-d interposers, which can be entered directly into cooling solutions without any barriers.An example provided by Intel is one involving a microprocessor connected directly to the stack memory.ODI avoids the full stack of two dies, thus providing direct coolant channels for both dies.At the same time, this version preserves the high-bandwidth foveros-like interconnect between bare chips, while eliminating the need for long channels through the silicon intermediary layer.


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On the surface, the Type 1 Cavity version appears to be very similar to the standard EMIB, but quite different.The ODI chips in this version are not actually embedded in the silicon and have routing capabilities all around them.The base ODI chip is placed in the cavity at a controlled height using hot pressing bonding.Then, TCB is used to fix the top die.By independently controlling the height of the bottom die, they were able to maximize the C4 process.


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Type 2: completely below the top Die


In ODI type 2, the die is completely below the top die.In this case, the bottom strip can be precisely positioned at the desired location, and the wiring path is closest to the required logic in the top strip, in much the same way that a side capacitor (LSC) is used.ODI2 can be used to enhance the advantages of top bare chips, for example by attaching other I/O features or local caching.Alternatively, it can be used to add another layer of primary functionality, such as by connecting the accelerator directly beneath the processor.


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Mix and Match

One of the interesting features of ODI is that all the various options can be mixed and matched where they make sense, as needed.For example, it is possible to make the base bare pieces larger to include multiple top bare pieces in the Type 2 configuration and the edge bare pieces in the Type 1 configuration so that their power transfer can escape through the copper column.


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Intel has introduced impressive new packaging technology involving a range of features and functions.It took years for chips like Kaby Lake G to be mass-produced before the EMIB was first revealed.Given that Intel first unveiled ODI in late 2019, it may be a few years before we see this technology.Probably within the 202/23 timeframe, but as EMIB and Foveros technologies mature, we are likely to see further integration of new technologies with features other than ODI and faster production.