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FPGA general reset pin will be connected to the global clock pin?

April 13, 2021


Everyone who has contact with FPGA knows that "reset" is simple and complicated. The simple reason is that when you learn, you only need to reset according to a fixed routine-the key switch, see the register and reset it at a low level first, so that 99% of the problems can be solved in general, and even simple design, there is no problem. The complexity is because the reset itself is an operation on a large-scale hardware unit, and the underlying design of the tube must be considered.

There are three common reset methods

1. Hardware switch: the reset signal is connected to a DIP switch or button, or RC circuit

2. Power chip: The power chip is generated when the power is turned on, and it can be maintained for a long time until it is stable.

3. Control chip: The control chip generates a reset pulse.

Reset pin

In theory, FPGA devices do not have a dedicated reset pin, and any general-purpose IO can be used as a reset input for FPGA logic functions. This is different from microcontrollers. For common FPGA development boards, buttons can be used as reset input. For example, on the AC6102 development board, there are 5 buttons, any of which can be used as a reset input. For the convenience of use, it is more convenient to use the button in the upper right corner as the reset button because it is far away from the other 4 buttons. It is not easy to be confused with other keys when designing functions. Users can also try to design the reset function on the other 4 buttons by themselves, and they all work normally.


Power-on reset is implemented.

Since it has been said that there is no dedicated reset pin on FPGA, when using a certain button as a reset pin, is it necessary to add common RC reset components to support power-on reset?

In fact, it is not necessary. One is because the FPGA has an initialization process after the configuration is completed. This process can realize the similar function of power-on reset to the reset pin we set. In addition, in a strict sense, FPGA logic code cannot adopt such conventional power-on reset ideas. The reason is that the configuration process must be performed first after the fpga is powered on. Only after the configuration process is over, the designed logic function will begin to run. The reset pin we are talking about is for the logic of normal operation. However, it takes at least 0.5 seconds to complete the configuration from power-on. For some larger FPGA devices, the configuration takes longer, which may be as long as several seconds. General RC power-on reset circuit, the time is also within 0.5 seconds, so the use of RC reset circuit for FPGA devices, in fact, may not have any meaning. That is, FPGA cannot use an external delay reset circuit, because the time is not enough and the FPGA logic is not ready yet, the power-on reset state is over.

For fpga, it is very simple to realize power-on reset, design a counter internally, release the reset signal and stop timing when the count is full. This can be ignored in basic experimental learning. Re-study can be done in the later complex system design. Using the button as the reset input is more to realize the external manual reset function.

So why is the reset pin generally connected to the global clock pin? The register of altera has an input port for automatic clearing, and the global clock can be used to enable the register to be reset "synchronously". The synchronization here means that it arrives at the same time. Because the global clock signal has low delay, low jitter, and high signal quality.