May 04, 2021
John Eble, Vice President of Marketing, Rambus Buffer Chips
Looking back on 2020, driven by new infrastructure, data centers are ushering in new opportunities for development. This trend accelerates the iteration of DDR to a new generation of faster and more efficient products. Major domestic manufacturers have deployed DDR5 memory and promoted its extensive commercialization. On July 14, 2020, JEDEC released the DDR5 SDRAM standard, marking the transition of the entire industry to DDR5 server dual in-line memory modules (DIMMs). DDR5 memory has brought a series of important improvements and is expected to help the next generation of servers achieve better performance and lower power consumption. The following are the five highlights of DDR5 memory.
Data transfer rate increased to 6.4 Gb/s
Lower voltage brings lower power consumption
The second major improvement of DDR5 memory is the drop in operating voltage (VDD), which in turn brings a corresponding reduction in power consumption. After adopting DDR5, the supply voltage of DRAM, buffer chip register clock driver (RCD) and data buffer (DB) drops from 1.2V to 1.1V. However, designers also need to pay attention when designing products. The decrease in working voltage (VDD) also means that the anti-interference margin will become smaller.
Brand new power supply architecture
The third major improvement of DDR5 memory is the power supply architecture, which is also one of the important changes. DDR5 DIMM transfers the power management from the motherboard to the memory module itself, and ensures a more refined system power load through an onboard 12V power management integrated circuit (PMIC). The circuit will output 1.1V working voltage (VDD), with better onboard power control to optimize signal integrity and anti-interference ability.
Channel architecture update
Another major change in DDR5 is the use of a new DIMM channel architecture. The bus of DDR4 DIMM is 72 bits, composed of 64 data bits and 8 error correction code bits. After adopting DDR5, each DIMM module has two channels. Each channel is 40 bits wide: including 32 data bits and 8 error correction code bits. Although the data bit width is the same as the previous generation, the total number is 64 bits, but the two channels of DDR5 are independent of each other, which can improve memory access efficiency. In addition, DDR5 brings a new feature of refreshing the same memory block. This command allows one memory block of each memory block group to be refreshed, while all other memory blocks remain open to continue normal operation. Therefore, the use of DDR5 not only means a substantial increase in speed, its higher efficiency will also amplify the advantages brought by the increase in data rate.
In the DDR5 DIMM architecture, there is an independent 40-bit wide channel on the left and right sides of the DIMM module, and the two channels share the registered clock driver. In DDR4, the registered clock driver provides two output clocks on each side. In DDR5, the registered clock driver provides four output clocks on each side. The highest density DIMM can be equipped with 4 DRAM memory banks, each of 5 DRAM memory (single-sided, half channel) is a group, which can receive its own corresponding independent clock. The architecture of each single-sided half-channel module corresponding to an independent clock can optimize signal integrity and help solve the problem of reduced anti-interference margin caused by lower VDD.
Support for higher capacity DRAM modules is the fifth highlight of DDR5 memory. Using DDR5 buffer chip DIMM, server or system designers can use up to 64Gb of DRAM capacity in a single die package mode. And DDR4 only supports up to 16Gb DRAM capacity in single die package (SDP) mode. DDR5 supports functions such as on-chip error correction code, error transparent mode, post-package repair and read-write CRC check, and supports higher capacity DRAM modules, which also means higher DIMM capacity. Therefore, the maximum capacity of DDR4 DIMM in a single die package is 64 GB, while the capacity of DDR5 DIMM in a single die package is as high as 256 GB, which is four times that of DDR4.
DDR5 has made major improvements and optimizations on the basis of its predecessor, DDR4, and has introduced a variety of design considerations related to increased speed and reduced voltage in the new memory standard, which has triggered a new round of signal integrity challenges . Designers will need to ensure that the motherboard and DIMM can handle higher signal speeds and check the signal integrity of all DRAM locations when performing system-level simulation. Fortunately, DDR5 memory interface chips provided by vendors such as Rambus can effectively reduce the host memory signal load, and enable the DRAM on the DIMM to have a higher speed and larger capacity without sacrificing latency performance.
Thankfully, Rambus's DDR5 register clock driver (RCD) improves the signal integrity of the command and address signals (CA) sent from the host memory controller to the DIMM. The buses of both channels lead to the register clock driver, and then fanned out to both sides of the DIMM, effectively reducing the CA bus load observed by the host memory controller. Rambus's DDR5 data buffer (DB) chip will reduce the effective load on the data bus, so that the DRAM on the DIMM has a larger capacity without sacrificing latency performance.
As a well-known signal integrity (SI) and power integrity (PI) leader in the industry, Rambus has been committed to providing solutions for the highest performance systems on the market for more than 30 years. The Rambus DDR5 memory interface chipset can help designers make full use of the advantages of DDR5 to deal with the signal integrity challenges brought by more data, the new CA bus and higher clock speeds.