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First look at Intel's six new technologies.

September 01, 2020

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It is reported that 10nm SuperFin technology will be used in Intel's next-generation mobile processor code-named "Tiger Lake", and the processor is in production at the same time, and its OEM products are expected to be listed in the holiday season.

In addition, Intel also released the next-generation CPU microarchitecture Willow Cove, Tiger Lake SoC architecture, and fully scalable Xe graphics architecture. These innovative architectures will also be used in markets such as consumer, high-performance computing, mobile clients and gaming applications.


At the same time, Intel’s chief architect Raja Koduri, and a number of Intel academicians and architects also gathered together to focus on the six technical pillars of process/package, architecture, memory/storage, interconnection, security, and software. Details New developments in related technologies are introduced.

01


10nm SuperFin technology: comparable to full node conversion


The 10nm SuperFin technology realizes the combination of enhanced FinFET transistors and Super MIM (Metal-Insulator-Metal) capacitors, which can provide enhanced epitaxial source/drain, improved gate technology, and additional gate spacing.


Intel claims that this technology is not only the most powerful single-node performance enhancement in Intel's history, but the performance it enhances is also comparable to full-node conversion.

It is understood that the SuperFin technology is mainly through 5 aspects of transistor process optimization, so as to achieve the performance improvement of the process technology:


1. Optimize the source and drain structure


SuperFin technology increases the extension of the crystal structure on the source and drain to increase strain while reducing resistance, thereby allowing more current to pass through the channel.


2. Improve the gate process


The improvement of the gate technology has further improved the channel mobility and accelerated the movement of charge carriers.


3. Increase extra grid spacing


By adding additional gate spacing options, higher drive currents can be provided for chip functions that require the highest performance.


4. Use new thin wall


Intel uses a new type of thin-wall barrier in the SuperFin process to reduce via resistance by 30% and further improve interconnect performance.


5. Increased capacitance


Compared with the industry standard, the SuperFin process increases the capacitance by 5 times in the same footprint, which not only reduces the voltage drop, but also improves the product performance.


It is understood that this technology is mainly realized through the new "High-K" (Hi-K) dielectric materials. This material can be stacked in ultra-thin layers only a few angstroms thick to form a repeating "superlattice" structure.

02


Willow Cove and Tiger Lake CPU architecture


Based on the 10nm SuperFin process and the latest processor technology, Intel has launched the next-generation CPU microarchitecture called "Willow Cove".


Compared with the Sunny Cove architecture released by Intel in 2018, the Willow Cove architecture achieves an improvement over inter-generational CPU performance on the basis of the former, thereby greatly enhancing frequency and power efficiency.


At the same time, the Willow Cove architecture introduces a redesigned cache architecture in the larger incompatible 1.25MB MLC, and enhances security through Control Flow Enforcement Technology.

On the other hand, Tiger Lake is Intel's first SoC architecture with a new Xe-LP (low power consumption) microarchitecture, which can optimize the CPU and AI accelerators to achieve further improvements in CPU, AI and graphics performance.

Specifically, the Tiger Lake SoC architecture mainly includes the following 8 features:


1. Brand new Willow Cove CPU core. The innovation based on 10nm SuperFin technology can significantly increase the frequency.


2. New Xe graphics architecture. There are as many as 96 execution units (EUs), greatly improving the performance efficiency per watt.


3. Power management. The self-service dynamic voltage frequency adjustment (DVFS) in the consistent structure improves the efficiency of the fully integrated voltage regulator (FIVR).


4. Structure and memory. The bandwidth of the consistent structure is increased by 2 times, about 86GB/s memory bandwidth, and the proven LP4x-4267, DDR4-3200, and LP5-5400 architecture functions.


5. The dedicated IP for Gaussian network accelerator GNA 2.0 can be used for low-power neural inference calculations and reduce CPU processing. At the same time, in the case of running audio noise suppression workload, the CPU utilization of GNA inference calculation is 20% lower than that of the CPU without GNA.


6. IO. Integrate TB4/USB4, and integrate PCIe Gen 4 on the CPU for low-latency, high-bandwidth device access to memory.


7. Display. Synchronous transmission bandwidth up to 64GB/s can support multiple high-resolution displays. Dedicated structure path to memory to maintain quality of service.


8. IPU6. It has 6 sensors with 4K 30-frame video, 27MP pixel image, up to 4K90 frame and 42MP pixel image structure function.

03


A variety of independent graphics cards and micro-architecture based on Xe graphics architecture


On this architecture day, Intel introduced in detail the fully scalable Xe graphics architecture.


Currently, Xe graphics architecture mainly includes four series, Xe-LP (low power consumption), Xe-HP, Xe-HPC and Xe-HPG.

1. Xe-LP is Intel's most efficient architecture for PC and mobile computing platforms. Its highest configuration EU unit is 96 groups, and has a new architecture design, including asynchronous calculation, view instancing, sampler feedback, updated media engine with AV1, and updated display engine Wait.


Xe-LP enables new end-user functions with instant game tuning (Instant Game Tuning), capture and streaming, and image sharpening.


In terms of software optimization, Xe-LP will also improve the driver through the new DX11 path and optimized compiler.


2. Xe-HP is a multi-tiled, highly scalable, high-performance architecture. It can provide data center-level, rack-level media performance, GPU scalability and AI optimization.


In addition, Xe-HP covers dynamic range calculations from one tile to two and four tiles, and functions similar to multi-core GPUs.


Based on this feature, Intel demonstrated on the spot that Xe-HP transcodes 10 complete high-quality 4K video streams at a rate of 60 FPS on a single block. At the same time, it also demonstrated the computational scalability of Xe-HP on multiple blocks.


It is understood that Intel’s first Xe-HP chip has completed the startup test in the laboratory.


Currently, Intel is testing Xe-HP with key customers, and plans to let developers use Xe HP through Intel DevCloud. At the same time, Xe HP related products will also be launched next year.


3. Xe-HPG is a new Xe micro-architecture variant launched by Intel this time, optimized for gaming. It combines Xe-LP's good performance and power consumption building blocks, and uses Xe-HP's scalability to perform stronger configuration and calculation frequency optimization for Xe-HPC.


At the same time, Xe-HPG also added a new GDDR6-based memory subsystem to improve cost performance, and will support accelerated ray tracing. Xe-HPG is expected to start shipping in 2021.

Intel will launch two independent graphics cards based on the Xe architecture and introduce two new functions, real-time game adjustment and game sharpening, in the Graphics Command Center (IGCC).


One is Intel's first DG1 discrete graphics card based on the Xe-LP architecture, mainly for PC devices. At present, the graphics card has entered the production stage and is expected to begin delivery in 2020 as planned.


At the same time, DG1 is available for early access users on Intel DevCloud, including DG1 library and toolkit, allowing users to use oneAPI to write DG1 related software in advance.


The second is Intel's Server GPU (SG1) for the data center field. It is understood that SG1 integrates 4 DG1s, which can improve the performance to the data center level with a small size to realize low-latency, high-density Android cloud games and video streaming.


The SG1 will be put into production soon and will be shipped later this year.

04


Two data center architectures: Ice Lake and Sapphire Rapids

1. Ice Lake


Ice Lake is the first 10nm-based Intel Xeon Scalable processor that can provide strong performance in terms of throughput and responsiveness across workloads.


In terms of technology, Ice Lake includes full memory encryption, PCIe Gen 4, 8 memory channels, and an enhanced instruction set that can speed up cryptographic operations. In addition, the Ice Lake series will also launch variants for network storage and the Internet of Things.


Ice Lake is expected to be launched at the end of this year.


2. Sapphire Rapids


Sapphire Rapids is the next-generation Xeon Scalable processor developed by Intel based on enhanced SuperFin technology. It can provide standard technologies such as DDR5, PCIe Gen 5, and Compute Express Link 1.1.


Intel mentioned that Sapphire Rapids will be used in the Argonne National Laboratory "Aurora Exascale" supercomputer system (Aurora Exascale), continuing Intel's built-in AI acceleration strategy, using an accelerator called Advanced Matrix Extension (AMX).


Sapphire Rapids is expected to start the first production shipments in the second half of 2021.


In addition, Intel continues to promote innovation in the field of FPGA technology. It is worth mentioning that Intel has the world's first next-generation 224G-PAM4 TX transceiver.

05


Next-generation hybrid architecture products


Intel's next-generation mixed-architecture client product is called Alder Lake, which will combine and optimize Intel's Golden Cove and Gracemont architectures to provide a better performance-to-power ratio.

06


Hybrid and combined packaging technology: test chips have been taped out


Currently, most traditional packaging technologies use thermocompression bonding (Thermocompression bonding) technology. As an alternative to thermocompression bonding technology, hybrid bonding technology can accelerate the realization of bump pitches of 10 microns and below, resulting in higher interconnect density, bandwidth and lower power.


As early as the second quarter of this year, Intel's test chips using hybrid packaging technology have been successfully taped out.

07


Software: OneAPI Gold version will be launched this year


In terms of software, Intel released the eighth version of oneAPI Beta as early as July this year, bringing new functions and improvements to distributed data analysis, including rendering performance, performance analysis, and video and thread library.


Intel mentioned on the Architecture Day that the oneAPI Gold version will be launched later this year, and will provide developers with solutions that guarantee product-level quality and performance in scalar, vector, matrix, and spatial architecture.

08


Conclusion: Intel's "loss" and "gain"


For some time in the past, the news that Intel’s 7nm CPU was postponed and the market value was surpassed by Nvidia for the first time has inevitably caused many doubts and concerns in the industry.


But from this architecture day, we can see that Intel still retains strong technical strength and confidence. At a time when Moore’s Law is gradually slowing down, through continuous innovation in the fields of CPU, GPU, FPGA, and architecture, packaging and software. , To open up a more diversified and multi-dimensional development path to meet the increasingly diversified computing needs.


This seems to be another point of view that Intel wants to express-promoting the development of Moore's Law is not only to improve the nano process technology, but also to expand the transistor process technology and architecture innovation horizontally to "More than Moore."


In Intel's view, people are now in a new era of intelligence, and it is also an era that "benefits everyone's trillion computing power."


Under the technological torrent caused by the new era, Intel’s six technology pillar strategies that have been put forward since 2018 have promoted product upgrades around process and packaging, architecture, memory and storage, interconnection, security, and software. This is undoubtedly the industry’s Innovative development provides an effective solution.


In the future, in an increasingly competitive environment, can Intel continue to lead the innovation and upgrading of the entire industry? We will wait and see.