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7nm wafers are coming! Samsung mass production 7LPP EUV process

October 19, 2018


Following TSMC's first 7+ nanochips using EUV lithography at the beginning of this month, Samsung also announced that it will release and gradually produce a variety of 7nm (UV) EUV chips. In order to catch up with TSMC's ecosystem, Samsung will also support its IP and EDA infrastructure and detail its packaging capabilities.

Wafer foundry manufacturers - TSMC and Samsung compete for advanced processes, who can first launch the first 7 nanometer wafers made with extreme ultraviolet (EUV) lithography?

Following TSMC's first 7+ nanochips using EUV lithography at the beginning of this month, Samsung also announced that it will release and gradually produce a variety of 7nm (UV) EUV chips. In order to catch up with TSMC's ecosystem, Samsung will also support its IP and EDA infrastructure and detail its packaging capabilities.

At this week's Samsung Tech Day in Silicon Valley, USA, Samsung announced the completion of the EUV's 7nm LPP (Low Power Plus) process, officially entered commercial mass production, and will also be based on this technology toward 5nm, 3nm in the future. go ahead. In addition, Samsung announced a 256-GByte RDIMM based on its 16-Gbit DRAM chip and plans to use a solid-state hard disk (SSD) with built-in Xilinx FPGA.

However, the 7nm commercial mass production is still the highlight of the event, coupled with the company's in-house development of the EUV mask detection system, which symbolizes a development milestone for Samsung.

Compared to its 10nm node, Samsung's 7LPP process can reduce wafer area by up to 40%, increase speed by 20%, and reduce power consumption by 50%. In addition, Samsung said it currently has 50 foundry partners, including Ansys, Arm, Cadence (with 7nm digital and analog design flow), Mentor, Synopsys and VeriSilicon, all said to use 7nm process shots.

The 7LPP process is said to have attracted a lot of interest, including customers such as Internet giants, Internet companies and Qualcomm. However, Samsung expects that customers will post relevant news as early as the beginning of next year.

Samsung's foundry marketing director Bob Stear said that since the introduction of EUV equipment at the Huacheng S3 plant earlier this year, the EUV system has been supporting the 250W light source. Current power levels increase production to 1,500 wafers/day. He said that since then, the EUV system has gradually reached the peak of 280W, and Samsung's goal is to further increase the power to 300W.

Samsung Huacheng S3 Factory EUV Production Line (Source: Samsung)

Stear pointed out that EUV requires fewer layers than traditional argon fluoride (ArF) systems, which reduces the cost and yield. However, the technology node still needs multiple exposures in the front-end process (FEOL).

Samsung developed its own system to compare and adjust the expected and actual reticle pattern to accelerate its EUV production. Since it is not clear whether it is as automated as a typical third-party inspection system, VLSI Research CEO G. Dan Hutcheson sees it more like a mask inspection system.

Samsung expects its 7nm node to pass the Grade 1 AEC-Q100 automotive standard by the end of the year. In terms of packaging, Samsung is developing a redistribution layer (RDL) interposer that can mount up to eight high-bandwidth memory (HBM) stacks on a single component. The company is also committed to embedding passive components in the substrate to save space in the data center wafer.

Samsung's foundry marketing director Bob Stear showcases 7nm EUV wafers produced by Samsung S3 (Source: EE Times)

EUV reticle film may be delayed by 5nm?

According to Handel Jones, chief executive of market research firm International Business Strategies (IBS), both Samsung and TSMC may only use EUV for both wafer layers in the 7nm phase, as reticle shrouds are still under development and have not been used to date. At 5nm, they are likely to extend EUV to 6 layers, but this will be at least until 2021, when the reticle film will have sufficient durability and optical transmission capacity.

Jones said: "Samsung is using the EUV process about six months in advance because they have been using the system in DRAM and logic processes, but TSMC is leading the way in using IP and tools, and there are more customer partnerships. Such as AMD, Apple, HiSilicon and Nvidia."

Another analyst said that Cisco was originally a customer of IBM's foundry business and is currently working with TSMC to develop a 7nm product. Qualcomm's 7nm design is expected to be handed over to TSMC and Samsung.

Despite this, Jones predicts that the revenue of this Korean giant is expected to reach $90 billion this year, and may even exceed $150 billion by 2027. From the growth of Samsung's memory business, Jones estimates that its DRAM and NAND sales will reach 50% and 45% respectively.

Samsung is expected to begin mass production of 5nm and 4nm nodes by June next year, and achieve breakthrough progress on the same technology. Stear said the PDK for this process node is expected to be released before the end of the year and will create another line for EUV next to the S3 plant.

These three process nodes will bring the contacts closer and eventually move over the gates to increase density and reduce metal spacing. This is one of Intel's previous approaches to its 10nm node, but it has not yet been mass-produced.

Stear said: "We are gradually dealing with contact-over-gates. As some have found, this is an intractable problem."

In May of this year, Samsung announced plans to switch to a gate-all-around (GAA) transistor, or nanosheet, for the 3nm node. The goal is to reduce the nominal voltage to a new low to continue to reduce power. The first version of the 0.1 PDK for the 3nm node is expected to be available in June this year.

Samsung introduces a series of in-house development of a series of packaging technology

Memory development blueprint

In its core memory business, Samsung said it is starting to use its 16-Gbit chip-made 256GB RDIMM. These cards can run at DDR4 speeds up to 3,200MHz, support 50ns read and write, and should be ready for production by the end of the year.

These memory chips are manufactured using a 1 year nanometer process released a year ago. However, it is not clear whether the next 1y process will be imported into EUV. However, Seong Jin Jang, director of Samsung DRAM development, pointed out that the subsequent 1z and 1a process nodes will use EUV more and more widely.

Samsung also showed eight DIMMs running on the AMD EPYC server. Compared to its existing 128GB card, which provides 3.8 million operations/second at 225W, these DIMMs can achieve 3.2 million operations per second at 170W.

In the end, Samsung's goal is to increase the DIMM to 768GBytes, which ultimately increases the HBM data rate from the current 307GB/s to 512GB/s. He added that GDDR6 graphics memory will increase from the current 18Gbits/s to 22Gbits/s, while LPDDR memory power consumption will drop from 24mW/GB to 12mW/GB, but he also revealed when it will be implemented.

In addition, Samsung announced plans to use the smart SSD of the embedded Xilinx Zynq FPGA to increase performance by 2.8x to 3.3x. These devices are suitable for a variety of databases, AI, video and storage applications.

The company said the SSD will provide a way to scale performance more easily without having to use a standard FPGA with an independent accelerator. These SSD products, which are still in the prototype stage, will use a variety of density and mid-range FPGAs.