Recently, I worked with an intern on a non-inverting configuration OPA191 op amp with a gain of 2V/V, a load of 10kΩ, and a supply voltage of +/-15V. Figure 1 shows the schematic of the design.
Figure 1: OPA191 schematic with non-inverting configuration] OPA191 schematic
I asked the intern to lay out the board for the design, and at the same time gave him general guidance on PCB layout (for example: to minimize the routing path of the board, try to keep the components tightly arranged to reduce the board footprint) Space), then let him design it himself. How difficult is the design process? In fact, there are several resistors and capacitors, isn't it? Figure 2 shows the layout he first tried to design. The red line is the path to the top of the board, and the blue line is the bottom path.
Figure 2: First Layout Attempt
Seeing his first layout attempt, I realized that the board layout was not as intuitive as I thought; I should at least do some more detailed guidance for him. He completely followed my advice in design: shortening the routing path and placing the parts closely together. However, there is still much room for improvement in this layout in order to reduce the parasitic impedance of the board and optimize its performance.
The next step is an improvement to the layout. The first improvement we made was to move resistors R1 and R2 to the inverting pin (pin 2) of the OPA191; this helps reduce the stray capacitance of the inverting pin. The op amp's inverting pin is a high impedance node and therefore has a high sensitivity. Longer trace paths can be used as wires to couple high frequency noise into the signal chain. PCB capacitance on the inverting pin can cause stability problems. Therefore, the contacts on the inverting pin should be as small as possible.
Moving R1 and R2 to pin 2 allows the load resistor R3 to be rotated 180 degrees, which brings the decoupling capacitor C1 closer to the positive supply pin (pin 7) of the OPA191. It is extremely important that the decoupling capacitor be as close as possible to the power supply pin. If the trace path between the decoupling capacitor and the power supply pin is long, the inductance of the power supply pin is increased, which degrades performance.
Another improvement we made was the second decoupling capacitor C2. The VCC and C2 via connections should not be placed between the capacitor and the power supply pin, but should be placed where the supply voltage must pass through the capacitor into the device power supply pin. Figure 3 shows how to move each part and guide hole to improve the layout.
Figure 3: Location of the various parts of the improved layout
After moving the parts to the new location, you can still make some other improvements. You can widen the trace path to reduce the inductance, which is equivalent to the size of the pad to which the trace path is connected. It is also possible to perfuse the top and bottom ground planes of the board to create a solid low impedance path for the return current. Figure 4 shows our final layout.
Figure 4: Final layout
The next time you lay out a printed circuit board, it is recommended that you follow the following layout conventions:
Minimize the connection of the inverting pins.
Place the decoupling capacitor as close as possible to the power supply pin.
If multiple decoupling capacitors are used, place the smallest decoupling capacitor closest to the power supply pin.
Do not place the via between the decoupling capacitor and the power supply pin.
Extend the routing path as much as possible.
Do not let the 90 degree angle appear on the trace path.
Prime at least one solid ground plane.
Do not give up a good layout in order to mark parts with silk screen.
In the above, we talked about the correct way to lay out the instrumentation amplifier (op amp) PCB and provided a series of good layout practices for reference. Next, we will explore the common mistakes when laying out instrumentation amplifiers (INAs) and then show how INA PCBs are properly laid out.
The INA is used in applications that require amplifying differential voltages, such as measuring the voltage across shunt resistors in high-side current sensing applications. Figure 5 shows the schematic of a typical single-supply high-side current sensing circuit.
Figure 5: High-side current sensing schematic
Figure 5 measures the differential voltage through RSHUNT, R1, R2, C1, C2, and C3 are used to provide common mode and differential mode filtering, R3 and C4 provide output filtering for U1 INA, and U2 is used to buffer the INA reference pin. R4 and C5 are used to form a low-pass filter that minimizes the noise introduced by the op amp to the INA reference pin.
Although the schematic layout in Figure 5 seems intuitive, it is very easy to make mistakes in the PCB layout, resulting in reduced circuit performance. Figure 6 shows three common mistakes that workers have when checking INA layouts.
Figure 6: INA common PCB layout
As can be seen from the above figure, the first error is the measurement of the differential voltage Rshunt through the resistor. It can be seen that the Rshunt to R2 line is shorter, so its resistance is less than the resistance of the Rshunt to R1 line. This difference in line impedance may introduce an input bias current into the INA that causes a differential voltage on the U1 input side. Since the task of the INA is to amplify the differential voltage, an unbalanced line on the input side may cause an error. Therefore, it is necessary to ensure that the INA input line is balanced and as short as possible.
The second error is about the INA gain setting resistor Rgain. The U1 pin to Rgain pad is longer than the actual required length, thus causing additional resistance and capacitance. Since the gain depends on the resistance between the INA gain setting pin, pin 1 and pin 8, the extra resistor may bring the wrong target gain. Since the gain setting pin of the INA is connected to the feedback section in the INA, additional capacitance may cause stability problems. Therefore, make sure that the line connecting the gain setting resistors should be as short as possible.
Finally, it may be necessary to improve the position of the buffer circuit reference pin. The reference pin buffer circuit is located far from the reference pin, which may increase the resistance of the reference pin, causing noise or other signals to couple into the line. The extra resistance on the reference pin may reduce the high common-mode rejection ratio (CMRR) provided by most INAs. Therefore, the reference pin buffer circuit should be placed as close as possible to the INA reference pin.
Figure 7: PCB layout after correcting three types of errors
In Figure 7, it can be seen that the line lengths of R1 and R2 to the shunt resistor are the same and a Kelvin connection is used. The gain setting resistor to the INA pin is as short as possible, and the reference buffer circuit is as close as possible to the reference pin.
If you want to lay out the PCB for the INA in the future, be sure to follow these guidelines:
Ensure that all lines on the input side are fully balanced;
Reduce line length and minimize capacitance on the gain setting pin;
Arrange the reference buffer circuit as close as possible to the INA reference pin;
Arrange the decoupling capacitor as close as possible to the power supply pin;
At least one solid ground layer is placed;
Don't sacrifice a good layout in order to use silkscreen for components;