X28C64P-25

The purpose of the DATA Polling feature in the X28C64 memory is to indicate to the host system that the byte write or page-write cycle has completed. It allows a simple bit test operation to determine the status of the X28C64, eliminating the need for additional interrupt inputs or external hardware. During the internal programming cycle, reading the last byte written will produce the complement of that data on I/O 7. Once the programming cycle is complete, I/O 7 will reflect true data. However, if the X28C64 is in a protected state and an illegal write operation is attempted, DATA Polling will not operate. On the other hand, the Toggle Bit feature in the X28C64 memory provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O 6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete, the toggling will cease, and the device will be accessible for additional read or write operations. The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device, making it especially helpful in arrays comprised of multiple X28C64 memories that are frequently updated. It can also provide a method for status checking in multiprocessor applications.

The access time for the X28C64 memory is 150ns.

The write cycle time for the X28C memory when performing a complete memory rewrite is 0.625 seconds.