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TLC555QDR

IC OSC SGL TIMER 2.1MHZ 8-SOIC

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See Product Specifications for product details.

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TLC555QDR

IC OSC SGL TIMER 2.1MHZ 8-SOIC

Orders over $200 are eligible for a limited edition Chinese-style gift.

Orders over $200 are eligible for a limited edition Chinese-style gift.

Orders over $1000 qualify for a $30 shipping fee waiver.

Orders surpassing $5000 enjoy waived shipping and transaction fees.

These offers are applicable to both new and existing customers and are valid from January 1st, 2024, to December 31st, 2024.

  • Manufacturer:

    TI

  • Datasheet:

    TLC555QDR datasheet

  • Package/Case:

    SOP-8

  • Product Category:

    IC Chips

  • RoHS Status: RoHS Status Lead free/RoHS Compliant

Submit your quote request now, and we expect to provide a quote within May 03, 2024. Place your order now, and we expect to complete the transaction within May 08, 2024. Ps:Time is according to GMT+8:00.

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Stock:65000 PCS

Our commitment is to deliver prompt quotations within 12 hours. For further assistance, please contact us at [email protected].

TLC555QDR Product Details



  • Very Low Power Consumption

− 1 mW Typ at VDD = 5 V

  • Capable of Operation in Astable Mode

  • CMOS Output Capable of Swinging Rail to Rail

  • High Output-Current Capability

    − Sink 100 mA Typ

    − Source 10 mA Typ

  • Output Fully Compatible With CMOS, TTL,and MOS

  • Low Supply Current Reduces Spikes

  • During Output Transitions

  • Single-Supply Operation From 2 V to 15 V

  • Functionally Interchangeable With the

  • NE555; Has Same Pinout

  • ESD Protection Exceeds 2000 V Per

  • MIL-STD-883C, Method 3015.2

  • Available in Q-Temp Automotive 

  • High Reliability Automotive Applications

    Configuration Control/Print Support

    Qualification to Automotive Standards

description

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering. While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555.


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