BQ4013MA-120

The control circuitry of the bq4013/Y ensures write protection during power-up/power-down cycles by constantly monitoring the VCC supply for a power-fail-detect threshold (VPFD). When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All outputs become high impedance, and all inputs are treated as "don't care." Additionally, if a valid access is in process at the time of power-fail detection, the memory cycle continues to completion. Write-protection takes place if the memory cycle fails to terminate within a specific time period (tWPT) . Furthermore, as VCC falls past the VPFD threshold and approaches 3V, the control circuitry switches to the internal lithium backup supply, which provides data retention until valid VCC is applied. After VCC ramps above the VPFD threshold, write-protection continues for a specific time (tCER) to allow for processor stabilization before normal memory operation resumes .

The key features of the bq4013/Y nonvolatile static RAM include data retention for at least 10 years without power, automatic write-protection during power-up/power-down cycles, conventional SRAM operation with unlimited write cycles, internal isolation of battery before power application, and an industry standard 32-pin DIP pinout

The CMOS bq4013/Y nonvolatile static RAM has a maximum data retention period without power of at least 10 years.