STK14C88-3NF45

The STORE cycle in the Simtek STK14C88-3 memory device can be initiated by executing sequential E controlled READ cycles from six specific address locations. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. It is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE will take place. The six consecutive addresses must be read in the order listed in the Hardware Mode Selection Table . The RECALL cycle in the Simtek STK14C88-3 memory device is initiated by performing a sequence of E controlled READ operations at specific addresses. To initiate the RECALL cycle, the following sequence of E controlled READ operations must be performed: Read address 0E38, Read address 31C7, Read address 03E0, Read address 3C1F, Read address 303F, and Read address 0C63 to initiate the RECALL cycle. The RECALL operation is a two-step procedure where the SRAM data is cleared first, and then the nonvolatile information is transferred into the SRAM cells. After the RECALL cycle time, the SRAM will be ready for READ and WRITE operations again. The RECALL operation does not alter the data in the nonvolatile elements, and the nonvolatile data can be recalled an unlimited number of times .

The purpose of the µF capacitor tied from VCAP to ground in the Simtek STK14C88-3 memory device is to guarantee the STORE operation, regardless of power-down slew rate or loss of power from "hot swapping" .

The Simtek STK14C88-3 memory device has the following features mentioned in the document: - 10mA Typical ICC at 200ns Cycle Time - Unlimited READ, WRITE, and RECALL Cycles - 1,000,000 STORE Cycles to nonvolatile elements (Commercial/Industrial) - 100-Year Data Retention in nonvolatile elements (Commercial/Industrial) - Single 3.3V + 0.3V Operation - Commercial and Industrial Temperatures - 32-Pin SOIC and DIP Packages - Two separate modes of operation: SRAM mode and nonvolatile mode - High-frequency bypass capacitor of approximately 0.1 µF connected between VCAP and VSS for noise considerations - Performs a READ cycle when E and G are low and W and HSB are high STK14C88-3.