ADSP-21262SKSTZ200

KEY FEATURES

At 200 MHz (5 ns) core instruction rate, the ADSP-21262 operates at 1200 MFLOPS peak/800 MFLOPS sustained performance whether operating on fixed or floating point data

400 MMACS sustained performance at 200 MHz

Super Harvard Architecture—three independent buses for dual data fetch, instruction fetch, and nonintrusive, zerooverhead I/O 

2M bits on-chip dual-ported SRAM (1M bit block 0, 1M bit block 1) for simultaneous access by core processor and DMA

4M bits on-chip dual-ported mask-programmable ROM (2M bits in block 0 and 2M bits in block 1)

Dual data address generators (DAGs) with modulo and bitreverse addressing

Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing

GENERAL DESCRIPTION

The ADSP-21262 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices Super Harvard Architecture. The ADSP-21262 is source code compatible with the ADSP-21160 and ADSP-21161 DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Single-Instruction, Single-Data) mode. Like other SHARC DSPs, the ADSP-21262 is a 32-bit/40-bit floating-point processor optimized for high precision signal processing applications with its dual-ported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI).

As shown in the functional block diagram, the ADSP21262 uses two computational units to deliver a 5 to 10 times performance increase over the ADSP-2106x on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21262 DSP achieves an instruction cycle time of 5 ns at 200 MHz. With its SIMD computational hardware, the ADSP-21262 can perform 1200 MFLOPS running at 200 MHz

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