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SuperFin transistor technology blessing, a new generation of Intel 10nm process and six technology strategies unveiled.

Published :8/15/2020 1:32:38 AM

Click Count:2103


The company also announced the details of the Willow Cove micro-architecture and the Tiger Lake SoC architecture for mobile clients, and for the first time introduced the fully scalable Xe graphics architecture. These innovative architectures can serve the consumer, high-performance computing and gaming application markets. Based on Intel's "decomposition design" approach, combined with advanced packaging technology, XPU products and software-centric strategy, Intel's product portfolio is committed to providing customers with leading products.

10nm SuperFin technology

● After years of improvements to FinFET transistor technology, Intel is redefining the technology to achieve the most powerful single-node performance enhancement in its history, bringing performance improvements comparable to full-node conversion. The 10nm SuperFin technology realizes the combination of Intel enhanced FinFET transistors and Super MIM (Metal-Insulator-Metal) capacitors. SuperFin technology can provide enhanced epitaxial source/drain, improved gate process and additional gate pitch, and achieve higher performance by:

Enhance the extension of the crystal structure on the source and drain to increase strain and reduce resistance to allow more current to pass through the channel

● Improve the gate process to achieve higher channel mobility, so that charge carriers move faster

● Provides additional gate pitch options to provide higher drive currents for chip functions that require the highest performance

● The use of a new thin-walled barrier reduces the via resistance by 30%, thereby improving interconnect performance

● Compared with industry standards, the capacitance has increased by 5 times in the same footprint, thereby reducing voltage drop and significantly improving product performance. The technology is realized by a new type of "High-K" (Hi-K) dielectric material, which can be stacked in ultra-thin layers with a thickness of only a few angstroms to form a repeating "superlattice" structure. This is a leading technology in the industry, ahead of the existing capabilities of other chip manufacturers.

● 10nm SuperFin technology will be used in Intel's next-generation mobile processor code-named "Tiger Lake". Tiger Lake is in production, and OEM products will be available in the holiday season.


Test chips using "Hybrid bonding" technology have been taped out in the second quarter of 2020. The traditional "thermocompression bonding" technology is used in most packaging technologies today, and hybrid bonding is an alternative to this technology. This new technology can accelerate the realization of bump pitches of 10 microns and below, providing higher interconnection density, bandwidth and lower power.

Willow Cove and Tiger Lake CPU architecture

Willow Cove is Intel's next-generation CPU microarchitecture. Willow Cove is based on the latest processor technology and 10nm SuperFin technology, and on the basis of the Sunny Cove architecture, it provides an improvement over inter-generational CPU performance, greatly improving frequency and power efficiency. It also introduces the redesigned cache architecture into the larger non-compliant 1.25MB MLC, and enhances security through Intel Control Flow Enforcement Technology.

Tiger Lake will provide intelligent performance and breakthrough progress in key computing vectors. Tiger Lake is the first SoC architecture to use the new Xe-LP graphics micro-architecture, which can optimize the CPU and AI accelerators, which will enable CPU performance to be improved beyond a generation, and achieve large-scale AI performance improvements and a huge leap in graphics performance , And a complete set of top IP in the entire SoC, such as the newly integrated Thunderbolt 4.

The Tiger Lake SoC architecture provides:

● The new Willow Cove CPU core-based on 10nm SuperFin technology advancement, significantly increase the frequency

● New Xe graphics architecture-with up to 96 execution units (EUs), performance efficiency per watt is significantly improved

● Power Management-Autonomous Dynamic Voltage and Frequency Adjustment (DVFS) in a consistent structure to improve the efficiency of the fully integrated voltage regulator (FIVR)

● Structure and memory-Consistent structure bandwidth increased by 2 times, about 86GB/s memory bandwidth, proven LP4x-4267, DDR4-3200; LP5-5400 architecture features 

● Gaussian network accelerator GNA 2.0 dedicated IP, used for low-power neural inference calculations, and reduce CPU processing. When running the audio noise suppression workload, the CPU usage of GNA inference calculation is 20% lower than that of the CPU without GNA

● IO-Integrated TB4/USB4, PCIe Gen 4 integrated on the CPU, used for low-latency, high-bandwidth device access to memory

● Display-Up to 64GB/s simultaneous transmission bandwidth is used to support multiple high-resolution displays. Dedicated structure path to memory to maintain quality of service 

● IPU6-up to 6 sensors, with 4K 30-frame video, 27MP pixel image; up to 4K90 frames and 42MP pixel image architecture function

Hybrid architecture

Alder Lake is Intel's next-generation client product with a hybrid architecture. Alder Lake will combine Intel's upcoming two architectures-Golden Cove and Gracemont, and will be optimized to provide excellent performance-to-power ratio.

Xe graphics architecture

Intel detailed the optimized Xe-LP (low-power) micro-architecture and software to provide efficient performance for mobile platforms. Xe-LP is Intel’s most efficient architecture for PC and mobile computing platforms, with a maximum configuration of up to 96 groups of EU units, and a new architecture design, including asynchronous computing, view instancing, and sampler feedback , An updated media engine with AV1 and an updated display engine, etc. This will enable new end-user features with instant game tuning (Instant Game Tuning), capture and streaming, and image sharpening. In terms of software optimization, Xe-LP will improve the driver through the new DX11 path and optimized compiler.

The first Xe-HP chip has been tested in the laboratory. Xe-HP is the industry's first multi-tiled, highly scalable, high-performance architecture that provides data center-level and rack-level media performance, GPU scalability, and AI optimization. It covers the calculation of dynamic range from one block to two and four blocks, and its function is similar to multi-core GPU. At the Architecture Day event, Intel demonstrated that Xe-HP transcodes 10 complete high-quality 4K video streams at a rate of 60 FPS on a single block. Another demonstration also showed the computational scalability of Xe-HP on multiple blocks. Intel is currently testing Xe-HP with key customers and plans to make Xe HP available to developers through Intel® DevCloud. Xe HP will be launched next year.

Intel launched a new variant of Xe microarchitecture-Xe-HPG, which is a microarchitecture optimized for games, combined with the building blocks of Xe-LP's good performance-to-power ratio, and leverages the scalability of Xe-HP Xe-HPC is configured more strongly and the calculation frequency is optimized. At the same time, Xe-HPG adds a new GDDR6-based memory subsystem to improve cost performance, and will have accelerated ray tracing support. Xe-HPG is expected to start shipping in 2021.

Intel® Server GPU (SG1) is Intel’s first Xe-based discrete graphics card for data centers. SG1 achieves the aggregation of 4 DG1s, which can improve the performance to the data center level in a small size to achieve low-latency, high-density Android cloud games and video streaming. The SG1 will be put into production soon and will be shipped later this year.

Intel's first discrete graphics graphics card DG1 based on the Xe architecture has been put into production and is expected to begin delivery in 2020 as planned. DG1 is now available for early access users on Intel® DevCloud. As disclosed at CES, DG1 is Intel's first discrete graphics card for PCs based on the Xe-LP microarchitecture.

● Intel® Graphics Command Center (IGCC) introduces new features, including real-time game adjustments and game sharpening.

Instant game adjustment is a game-specific driver that can push repairs and optimizations to end users faster than before, and does not require downloading and installing complete drivers. It only requires users to choose to join once in each game.

● Game sharpening uses perceptual adaptive sharpening, an adaptive sharpening algorithm based on computational shaders to improve image clarity in games. This feature is especially useful for games that use resolution scaling to balance performance and image quality, and is an optional feature in IGCC.

Data center architecture

Ice Lake is the first Intel Xeon Scalable processor based on 10nm and is expected to be launched by the end of 2020. Ice Lake products will provide strong performance in terms of throughput and responsiveness across workloads. It will bring a series of technologies, including full memory encryption, PCIe Gen 4, 8 memory channels, etc., and an enhanced instruction set that can speed up cryptographic operations. Variants for network storage and the Internet of Things will also be introduced in the Ice Lak series.

Sapphire Rapids is Intel's next-generation Xeon Scalable processor based on enhanced SuperFin technology. It will provide leading industry standard technologies, including DDR5, PCIe Gen 5, Compute Express Link 1.1, etc. Sapphire Rapids will be the CPU used in the "Aurora Exascale" supercomputer system (Aurora Exascale) of the Argonne National Laboratory. It will continue Intel's built-in artificial intelligence acceleration strategy and use a new type called Advanced Matrix Extension (AMX). accelerator. Sapphire Rapids is expected to start the first production shipments in the second half of 2021.

Intel now has the world's first next-generation 224G-PAM4 TX transceiver, demonstrating its continuous innovation in advanced FPGA technology and its leading position in the field of three consecutive generations of transceivers.


The oneAPI Gold version will be launched later this year, providing developers with solutions that guarantee product-level quality and performance in scalar, vector, matrix and space architecture. Intel released its eighth version of oneAPI Beta in July, bringing new features and enhancements to distributed data analysis, including rendering performance, performance analysis, and video and thread library. DG1 discrete GPU is currently available to some developers on Intel® DevCloud, which includes DG1 libraries and toolkits to enable them to start writing DG1 related software using oneAPI before they own the hardware.

The various technological innovations this time revealed the continuous progress of Intel's innovation strategy of "six technological pillars". Intel is making full use of its unique advantages to provide solutions that combine scalar, vector, matrix, and spatial architectures, which are widely deployed in CPUs, GPUs, accelerators and FPGAs, and are unified by the open, industry-standard programming model oneAPI. This simplifies application development.