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XC3042-100PG132B Image

Images are for reference only.

See Product Specifications for product details.


Field Programmable Gate Array (FPGA)

Xilinx, Inc
XC3042-100PG132B PDF
Product Category:
IC Chips
15 PCS

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Product Parameter

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
New & Original - Factory Package
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No Limit for XC3042-100PG132B
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XC3042-100PG132B Product Details



● Enhanced,high performance FPGA family with five device types

   - lmproved redesign of the basic xc3000 FPGA farmily

   - Logic densities from 1,0o0 to 6,000 gates

   - Up to 144 user-definable l/Os

● Superset of the industry-leading xC3000 family

   - ldentical to the basic xc30oo in structure, pin out, design methodology,and software tools

   - 100% compatible with all XC3000, XC3000L, and XC3100A bitstreams

   - lmproved routing and additional features

● Additional programmable interconnection points (PIPs)

   - lmproved access to longlines and CLB clock enable inputs

   - Most efficient xC30o0-class solution to bus-oriented designs

● Advanced o.8u and 0.6u CMos static memory technology

   - Low quiescent and active power consumption

● Performance specified by logic delays, faster than corresponding xc30o0 versions

● XC3000A-specific features

   - 4 mA output sink and source current

   - Error checking of the configuration bitstream

   - Soft startup starts all outputs in slew-limited mode upon power-up

   - Easy migration to the xC3400 series of HardWire mask programmed devices for high-volume production.


The xc3000A family offers the following enhancements over the popular xC3000 family:

The xC300oA family has additional interconnect resources to drive the l-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline.These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing.

During configuration,the xC3000A devices check the bitstream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls lNIT Low.

When the configuration process is finished and the device starts up in user mode,the first activation of the outputs is automatically slew-rate limited. This feature,called Soft Startup, avoids the potential ground bounce when all outputs are turned on simultaneously.After start-up,the slew

rate of the individual outputs is, as in the XC3000 family, determined by the individual configuration option.

The XC3000A family is a superset of the XC3000 family. Any bitstream used to configure an XC3000,XC3100 or

XC3100A device configures an XC3000A device exactly the same way.


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