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SN74HC138DT

3-Line To 8-Line Decoders/Demultiplexers

SN74HC138DT
  • SN74HC138DT
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SN74HC138DT

3-Line To 8-Line Decoders/Demultiplexers

Orders over $200 are eligible for a limited edition Chinese-style gift.

Orders over $200 are eligible for a limited edition Chinese-style gift.

Orders over $1000 qualify for a $30 shipping fee waiver.

Orders surpassing $5000 enjoy waived shipping and transaction fees.

These offers are applicable to both new and existing customers and are valid from January 1st, 2024, to December 31st, 2024.

  • Manufacturer：

    TI

  • Datasheet：

    SN74HC138DT datasheet

  • Package/Case：

    SOIC-16

  • Product Category：

    Linear - Analog Multipliers, Dividers

  • RoHS Status：

Submit your quote request now, and we expect to provide a quote within April 19, 2024. Place your order now, and we expect to complete the transaction within April 23, 2024. Ps:Time is according to GMT+8:00.

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Stock：500 PCS

Our commitment is to deliver prompt quotations within 12 hours. For further assistance, please contact us at [email protected].

SN74HC138DT Product Details

1 Features

● Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems

● Wide Operating Voltage Range (2 V to 6 V)

● Outputs Can Drive Up To 10 LSTTL Loads

● Low Power Consumption, 80-μA Maximum lcc

● Typicaltpo= 15 ns

● ±4-mA Output Drive at 5 V

● Low Input Current of 1-μA Maximum

● Active Low Outputs ( Selected Output is Low)

● Incorporate Three Enable Inputs to Simplify Cascading or Data Reception

2 Applications

● LED Displays

● Servers

● White Goods

● Power Infrastructure

● Building Automation

● Factory Automation

3 Description

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

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