LPC1776FBD208

1. General description

The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation.

The Cortex-M3 is a next generation core that offers better performance than the ARM7 at the same clock rate and other system enhancements such as modernized debug features and a higher level of support block integration. The Cortex-M3 CPU incorporates a 3-stage pipeline and has a Harvard architecture with separate local instruction and data 

buses, as well as a third bus with slightly lower performance for peripherals. The Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branches. 

The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. The LPC178x/7x is targeted to operate at up to 120 MHz CPU frequency.

The peripheral complement of the LPC178x/7x includes up to 512 kB of flash program memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory, External Memory controller (EMC), LCD (LPC178x only), Ethernet, USB Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers, three I2C-bus interfaces, one eight-channel, 12-bit ADC, a 10-bit DAC, a Quadrature 

Encoder Interface, four general purpose timers, two general purpose PWMs with six outputs each and one motor control PWM, an ultra-low power RTC with separate battery supply and event recorder, a windowed watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins, and more. The pinout of LPC178x/7x is intended to allow pin function compatibility with the LPC24xx and LPC23xx.

2. Features and benefits

 Functional replacement for LPC23xx and 24xx family devices.

 System:

 ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A Memory Protection Unit (MPU) supporting eight regions is included.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, and General Purpose DMA controller. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time.

 Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy.

 Cortex-M3 system tick timer, including an external clock input option.

 Standard JTAG test/debug interface as well as Serial Wire Debug and Serial WireTrace Port options.

 Emulation trace module supports real-time trace.

 Boundary scan for simplified board testing.

 Non-maskable Interrupt (NMI) input.

3. Applications

 Communications:

 Point-of-sale terminals, web servers, multi-protocol bridges

 Industrial/Medical:

 Automation controllers, application control, robotics control, HVAC, PLC, inverters, circuit breakers, medical scanning, security monitoring, motor drive, video intercom

 Consumer/Appliance:

 Audio, MP3 decoders, alarm systems, displays, printers, scanners, small appliances, fitness equipment

 Automotive:

 After-market, car alarms, GPS/fleet monitors

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